Not Applicable.
Not Applicable.
The present embodiments relate to modems, and are more particularly directed to frame synchronization in wireline modems.
The high-speed exchange of digital information between remotely located computers is now a pervasive part of modem computing in many contexts, including business, educational, and personal computer uses. It is contemplated that current and future applications of high speed data communications will continue the demand for systems and services in this field. For example, video on demand (xe2x80x9cVODxe2x80x9d) is one area which has for some time driven the advancement of technology in the area of digital information exchanges. More recently, the rapid increase in use and popularity of the Global Internet has further motivated research and preliminary development of systems directed to advanced communication of information between remotely located computers, particularly in accomplishing higher bit rates using existing infrastructure.
Various types of modems have been and continue to be developed to achieve the high speed data communication arising from matters such as those described above. For example, ISDN modems typically transmit and receive data at speeds of 64 Kbps and 128 Kbps. As another example, cable modems are currently under development with the promise of data connections of much higher speeds than ISDN. More particularly, cable modems are anticipated to receive data at up to 10 Mbps and send data at speeds up from 2 to 10 Mbps. Still other modems are also known in the art.
Given the proliferation of wireline modems, many such modems use frame structures to communicate information. By way of example, therefore, FIG. 1 illustrates such a frame designated generally at 10. By way of example, frame 10 is a quadrature amplitude modulation (xe2x80x9cQAMxe2x80x9d) frame, where it is known in the art that QAM frames encode data in an analog signal which includes one of a different available combination of phases and amplitudes to represent different bit patterns. Within frame 10 is provided training data 12 to tune an equalizer in the receiving modem. In order to locate training data 12, frame 10 also includes a synchronization or xe2x80x9csyncxe2x80x9d sequence 14 placed at the start of frame 10. As a result, a receiving modem must recognize sync sequence 14 at some point during the receipt of frame 10. Once this recognition occurs, it may be determined where the beginning of the frame is located, and it thus will be known where the end of sync sequence 14 occurs. Knowing the location of the end of sync sequence 14 thereby identifies the location of the beginning of training data 12. Additionally, frame 10 includes user data 16 located after training data 12 and, thus, by locating the position of training data 12, the location of user data 16 also may be determined.
By way of further background, FIG. 2 illustrates a block diagram of a receiver path in a modem 18. The block diagram of modem 18 is a general representation and, thus applies in general to the prior art but also may be modified as described later to form an inventive embodiment. Modem 18 receives frame data as an analog signal from a wireline (e.g., a telephone line or a cable, such as a coax cable), and that data is input to an analog-to digital converter (xe2x80x9cADCxe2x80x9d) 20 where it is converted to a digital form. The digitally converted signal then passes to a timing recovery block 22 that re-times the sampling of the input waveform so that the receive sampling frequency tracks that of the transmitter in frequency. Next, the signal passes to a demodulator 24 that removes the data from its modulated form, thereby producing the baseband values of the data. Note that the frequency of the baseband value signal output from demodulator 24 is typically at some integer multiple (or other fraction greater than one) of the symbol rate; commonly, therefore, the output of demodulator 24 is at two times the symbol rate. From the output of demodulator 24, the demodulated data passes to both a sync block 26 as well as an equalizer and carrier recovery block 28. Sync block 26 locates sync sequence 14 in each frame as detailed below, and when this location occurs sync block 26 asserts a SYNC signal to equalizer and carrier recovery block 28 so that it may synchronize itself to the incoming signal and perform training. Equalizer and carrier recovery block 28 outputs the equalized signal to a symbol decision block 30. Symbol decision block 30 performs the function of estimating the transmitted data from the output of equalizer and carrier recovery block 28. This is usually performed by finding the nearest point in the signal constellation to each received sample. This result is output to a deframer 32. In addition, symbol decision block 30 feeds back a signal to equalizer and carrier recover block 28 in order to provide decision-directed tracking of changes in the channel during the data portion of the frame. Lastly, note that, the SYNC signal from sync block 26 is also connected to deframer 32 so that it too may synchronize itself to the incoming signal. Further, deframer 32 performs the function of removing training data 12 and sync sequence 14 from frame 10, thereby leaving only user data 16.
Looking now to sync block 26 in greater detail, it locates sync sequence 14 in each frame 10 by taking periodic samples, where this approach is now described with the benefit of a general timing illustration in FIGS. 3a and 3b. Specifically, in FIG. 3a, let the points P0 through P3 represent successive ideal sample locations in sync sequence 14, with a common time period T between each location. In other words, in an ideal situation, sync block 26 would sample the incoming signal at the exact point in time corresponding to point P0; in the art, this point is sometimes referred to as the center of a so-called eye diagram, with it understood that an actual sample taken at this ideal point is most likely to result in proper synchronization, and any increase in time between this ideal point and the actual sample point correspondingly decreases the synchronization performance (i.e., decreases the chance of successful synchronization). Additionally, given the sampling period T, sync block 26 then also ideally samples at each interval of T thereafter, thereby sampling exactly at the points P1, P2, and P3 illustrated in FIG. 3a. However, various factors cause sync block 26 to take actual samples at a phase shifted point in time which is away from that of each point in FIG. 3a. Such factors include the fact that there is no common clock or timing signal for synchronization between the transmitter and the receiver, and also may include other factors such as channel distortion and carrier errors. By way of example, therefore, FIG. 3b again illustrates points P0 through P3, and further illustrates a first scenario where a first actual sample S0 is taken, followed thereafter by additional samples at each period of T thereafter. Thus, samples are taken at times represented as S0, S1, S2, and S3. As the samples are taken, a technique is used whereby the samples are convolved with a filter correlation sequence that represents a time reversed, complex conjugate of sync sequence 14. As a result, the convolution determination will peak when sync sequence 14 is aligned with the filter correlation sequence. Also in this regard, in an effort to produce the greatest possible peak, note that sync sequence 14 is typically formed by selecting from the four highest energy points of the symbol constellation and, indeed, using only the two of those four points that have the greatest spectral distance between them (i.e., xe2x88x9215xe2x88x92jmax+15+jmax for QAM). Given these considerations, the convolution peak may be detected by comparing the convolution result against a threshold, where the threshold is set to a level just below the anticipated maximum peak. Accordingly, when the threshold is exceeded, sync block 26 asserts its SYNC output, thereby informing other blocks in FIG. 2 that synchronization has occurred.
While the preceding approach may prove acceptable in some contexts, note further in FIG. 3b that a length of time (or phase shift), indicated in FIG. 3b as xcex4, occurs between each ideal sampling point and a corresponding actual sample. In other words, in FIG. 3b xcex4 is a length representing a distance between the ideal sampling time and the actual sampling time. Moreover, because of this time separation, note that the peak of the convolution may be less than the anticipated peak. As a result, under the prior art approach it may be required that the threshold used for comparison is lowered to accommodate the lower corresponding peak. However, if the threshold is set too low, then it may be exceeded in some instances when an actual sync sequence has not been detected, which in turn could cause errant assertions of the SYNC output of sync block 26. Quite clearly, these errant assertions of the SYNC output may cause wrongful interpretation of incoming data.
Given the preceding, it has been recognized by the present inventor that the length of xcex4 directly affects the likelihood that the prior art system will properly detect sync sequence 14 in an incoming frame. Additionally, for systems of the type shown in FIG. 2, a maximum value of xcex4, designated from this point forward as xcex4max, may be determined empirically under which proper synchronization detection is ensured (or at least expected to meet an accepted confidence level). To further illustrate this point, assume by way of example that xcex4max is determined empirically to equal T/4. This example is further illustrated in FIG. 4. More particularly, FIG. 4 once more illustrates points P0 through P3. Additionally, because xcex4max equals T/4, then proper operation should occur so long as the sample for each point occurs within a time period no greater than T/4 before or after each such point. To further illustrate these periods of anticipated proper operation, a sampling window of time having a period from T/4 before the point to T/4 after the point is shown with respect to each of points P0 through P3, labeled for reference as SW0 through SW3, respectively. Having defined sampling windows SW0 through SW3, there also are periods of time that do not fall within these sampling widows. Given the preceding definitions, therefore, these periods of time represent instances where, if sampling occurs, proper sync detection may not occur. These periods are shown as error windows EW0 through EW3 in FIG. 4. Note that each error window occurs beyond both edges of the sample window, that is, because the sample window is by definition centered about the point, then each point will have two corresponding error windows, one before and one after the sample window. Thus, in FIG. 4, it is noted that the second instance of error window EW0 following point P0 coincides with a first instance of error window EW1 preceding point P1. A similar observation may be made regarding the remaining sample and error windows.
From the above, the present inventor notes that the prior art may provide various drawbacks. For example, for a given system, if xcex4max is relatively short, then the error windows EW0 through EW3 are relatively large. Accordingly, the chance of the periodic samples falling within error windows EW0 through EW3 are likewise increased, thereby increasing the likelihood of faulty sync detection, where faults may include both errant indication of synchronization or a total failure to achieve synchronization. Certain attempts may be made to reduce the chances of error by increasing the length of xcex4max, such as by increasing the number of symbols in sync sequence 14. However, such an approach thereby reduces the bandwidth available for user data and, thus, may be undesirable. Consequently, this as well as other efforts may require greater resources (and cost), or simply may not be acceptable or feasible in various contexts. As a result, there arises a need to address the drawbacks of the prior art, as is achieved by the embodiments described below.
In the preferred embodiment, there is a modem. The modem comprises circuitry for receiving an analog signal from a line and circuitry for converting the analog signal to a digital signal. The digital signal comprises a plurality of ideal sample points, each separated in time by a period T, and the plurality of ideal sample points comprises a sync sequence. The modem further comprises circuitry for detecting the sync sequence, comprising an integer number S of sampling circuits, where S is two or greater. Each of the sampling circuits comprises circuitry for taking a sample corresponding to each of the plurality of ideal sample points at least once per the period T. Each of the sampling circuits also comprises circuitry for comparing a plurality of taken samples to a correlation sequence. Finally, each of the sampling circuits comprises circuitry for outputting a sync detected signal in response to a sufficient match between the plurality of taken samples and the correlation sequence. Other circuits, systems, and methods are also disclosed and claimed.